Semiconductor devices are manufactured by depositing many different types of material layers over a semiconductor workpiece or wafer, and patterning the various material layers using lithography. The material layers typically comprise thin films of conductive, semiconductive, and insulating materials that are patterned to form integrated circuits (IC's). In many integrated circuit designs, the various material layers are planarized before depositing subsequent material layers, e.g., in order to remove excess material from the surface of the wafer.
There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single semiconductor die or chip. Semiconductor technology has experienced a trend towards miniaturization, to meet the demands of product size reduction, improved device performance, and reduced power requirements in the end applications that semiconductors are used in, for example.
In the past, integrated circuits contained only a relatively small number of devices per chip, and the devices could be easily interconnected. However, in more recent integrated circuit designs, there may be millions of devices on a single chip, resulting in the need for multilevel interconnect systems, wherein the area for interconnect lines is shared among two or more material levels.
As the number of interconnect layers in integrated circuits has increased, the planarization of dielectric and metal layers has become more critical, for example. In the past, planarization techniques such as thermal flow, sacrificial-resist etch-back, and spin-on glass were adequate to planarize interconnect systems. However, these techniques provide only a limited degree of smoothing and local planarization. For global planarization of a semiconductor wafer, chemical-mechanical polishing (CMP) is typically used.
In most CMP processes, an abrasive material is used to planarize a wafer. The abrasive may be disposed in a slurry, or the abrasive material may be fixed to a polishing pad, for example.
In a CMP process, elevated features on the wafer are selectively removed, e.g., material from higher elevation features is removed more rapidly than material at lower elevations, resulting in reduced topography. The process is referred to as “chemical-mechanical polishing” because material is removed from the wafer by mechanical polishing, assisted by chemical action.
What are needed in the art are improved CMP and polishing processes and apparatus.